Download at MAXIMUM SPEED and remove 503 Error

Purchase a VIP membership and download using our fastest servers, up to 1Gb/s
If you get 503 error while downloading, Become VIP to download with unlimited connections.

Description

Learn VHDL and FPGA Development A tutorial film on how to create a VHDL design from Udemy. Created VHDL designs can be simulated and implemented on a Xilinx or Altera FPGA development page. The VHDL and FPGA development course is a course designed to teach students how to create successful VHDL simulations. The course includes 20 lessons that will teach students the syntax and structure of VHDL. By watching videos in this course, the student is able to understand the syntax and use of VHDL-specific keywords.

Features of Learn VHDL and FPGA Development:

  • VHDL design simulation using ModelSim
  • Debugging a VHDL design using ModelSim
  • Learn how to use the Xilinx ISE tool for the FPGA program
  • Understand the design process for executing a digital design on the FPGA
  • Learn how to simulate a design in ModelSim Altera and Xilinx Isim

Course specification:

  • Duration: 13:21:48 hours
  • English language
  • Number of courses: 91
  • Movie format: AVC 1280 × 720
  • Audio: AAC, 44.1 KHz, 2 Ch
  • Tutor: Jordan Christman

Topics in this course:

Curriculum For This Course
91 Lectures
13:21:48

Contact Information
2 Lectures 00:12

Introduction
2 Lectures 09:35

VHDL Data Types
8 Lectures 36:28

VHDL Syntax
7 Lectures 31:45

VHDL Coding Structure
6 Lectures 23:16

Test Bench
3 Lectures 9:55

Implementing State Machines in VHDL
2 Lectures 4:55

FPGA Development Boards
8 Lectures 12:41

Altera Tools
3 Lectures 11:43

Xilinx Tools
5 Lectures 20:08

Lab 1 – Full Adder
4 Lectures 32:36

Lab 2 – Shift Register
4 Lectures 08:29

Lab 3 – Universal Shift Register
5 Lectures 34:04

Lab 4 – 7 Segment Display
4 Lectures 14:07

Lab 5 – Counter
4 Lectures 08:24

Lab 6 – Multiplier
4 Lectures 16:25

Lab 7 – RC Servo
4 Lectures 25:18

Lecture Notes
14 Lectures 00:00

Extra References
2 Lectures 00:00

Course prerequisites

  • Buy BASYS 3 or BASYS 2 FPGA Development Board
  • Download Xilinx ISE webpack if you are using BASYS 2, but we will cover that in this course!
  • Download Vivado if your using the BASYS 3 board, we will cover this in the course!
  • Basic understanding of Binary Notation
  • Basic understanding of Hexadecimal Notation
  • Basic understanding of Logic Gates

Pictures

Learn VHDL and FPGA Development

Installation guide

After Extract with the required Player see.

This tutorial has English subtitles.

download link

Download part 1 – 1 GB

Download part 2 – 949 MB

File password (s): www.downloadly.ir

Size

1.92 GB

Leave a Reply

Your email address will not be published. Required fields are marked *

Fill out this field
Fill out this field
Please enter a valid email address.
You need to agree with the terms to proceed

Menu